VLSI-Algorithm Design of Convolutional-Neural-Network (CNN) Hardware Accelerator for Edge Application.
Digital VLSI-Architecture Design of Efficient Neural-Network inference engine for Edge Applications.
Application-Specific Integrated Circuit (ASIC) Chip Design, Implementation, Testing and Field-Programmable Gate Array (FPGA) prototyping for digital processing tasks in Artificial Intelligence, Post Quantum cryptography, Encryption accelerators, High Efficiency Video Codec, Wireless Communication System, Power Electronics, and Computer Arithmetic.
Testing of Neural-Network inference engine by developing a test-bed based on practical object classification scenario using FPGA and ASIC platform & software environment.
Awards & Fellowships
2024 - VLSID Fellowship, awarded with IEEE VLSID-2024 fellowship to attend tutorials and main conference at 37th IEEE International Conference on VLSI Design and 23rd International Conference on Embedded systems, Kolkata, India, Jan 5-10, 2024.
2023 - VLSID Fellowship, awarded with IEEE VLSID-2023 fellowship to attend tutorials and main conference at 36nd IEEE International Conference on VLSI Design and 22th International Conference on Embedded systems, Hyderabad, India, Jan 8-12, 2023.
2019 - MHRD HTRA fellowship to persue PhD from IIT Mandi
2016 - GATE Fellowship , Received full fellowship to pursue M.Tech from NIT Meghalaya
Memberships
Member, Institute of Electrical and Electronics Engineers (IEEE).
